Digital Circuits Cheatsheet
Latches and Flip-Flops
Use this Digital Circuits reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.
Overview
Latches and flip-flops are the fundamental memory elements of sequential logic. Unlike combinational circuits, they store a state bit. The key distinction: a latch is level-sensitive; a flip-flop is edge-triggered.
SR Latch (Set-Reset)
Built from cross-coupled NOR (or NAND) gates. The basic bistable memory element.
NOR-based SR Latch
| S | R | Q | Q′ | State |
|---|---|---|---|---|
| 0 | 0 | Q_prev | Q′_prev | Hold (memory) |
| 1 | 0 | 1 | 0 | Set |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 1 | 0 | 0 | Forbidden (invalid) |
Q and Q′ are supposed to be complements; S=R=1 violates this.
NAND-based SR̄ Latch (active-LOW inputs)
| S̄ | R̄ | Q |
|---|---|---|
| 1 | 1 | Hold |
| 0 | 1 | Set (Q=1) |
| 1 | 0 | Reset (Q=0) |
| 0 | 0 | Forbidden |
Gated (Clocked) SR Latch
Adds an enable (EN/CLK) input. Inputs S and R only affect Q while EN=1.
| EN | S | R | Q_next |
|---|---|---|---|
| 0 | X | X | Q (hold) |
| 1 | 0 | 0 | Q (hold) |
| 1 | 1 | 0 | 1 (Set) |
| 1 | 0 | 1 | 0 (Reset) |
| 1 | 1 | 1 | Forbidden |
D Latch (Data / Transparent Latch)
Eliminates the forbidden state by tying R = S′.
| EN | D | Q_next |
|---|---|---|
| 0 | X | Q (hold) |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
When EN=1 the output Q follows D (transparent). When EN=0 the last value is held.
Used in: 74HC373 (octal D latch), address latches in microprocessors.
D Flip-Flop (Edge-Triggered)
Q changes only on the active clock edge (rising ↑ or falling ↓), not during the entire clock level.
Positive-edge triggered D flip-flop
| CLK | D | Q_next |
|---|---|---|
| ↑ | 0 | 0 |
| ↑ | 1 | 1 |
| 0, 1, ↓ | X | Q (no change) |
Setup time (tₛ): D must be stable for tₛ before the clock edge. Hold time (tₕ): D must remain stable for tₕ after the clock edge. Propagation delay (tₚ): time from clock edge to Q settling.
JK Flip-Flop
Like SR but the J=K=1 condition causes Q to toggle instead of being forbidden.
| J | K | Q_next |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | 0 (Reset) |
| 1 | 0 | 1 (Set) |
| 1 | 1 | Q′ (Toggle) |
Characteristic equation: Q_next = J·Q′ + K′·Q
Race condition: In a level-triggered JK latch with J=K=1, Q oscillates. Edge triggering eliminates this.
T Flip-Flop (Toggle)
Special case of JK where J=K=T.
| T | Q_next |
|---|---|
| 0 | Q (hold) |
| 1 | Q′ (toggle) |
Characteristic equation: Q_next = T ⊕ Q
Primarily used in counters (T=1 → toggles on every clock edge).
Flip-Flop Comparison
| Type | Inputs | Forbidden state | Common use |
|---|---|---|---|
| SR | S, R | S=R=1 | Debounce circuits |
| D | D | None | Registers, pipeline stages |
| JK | J, K | None (toggle) | Versatile, counters |
| T | T | None | Counters, frequency dividers |
Flip-Flop Characteristic Equations
| FF | Q_next |
|---|---|
| D | D |
| T | T ⊕ Q |
| SR | S + R′·Q (subject to the constraint S·R = 0) |
| JK | J·Q′ + K′·Q |
Flip-Flop Excitation Tables
Used in sequential circuit design (what inputs are needed to achieve a desired state transition).
D Flip-Flop
| Q | Q_next | D |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
D = Q_next (simplest — just load what you want)
T Flip-Flop
| Q | Q_next | T |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
T = Q ⊕ Q_next
JK Flip-Flop
| Q | Q_next | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
X = don't care (use to simplify K-map expressions)
Asynchronous Inputs
| Input | Active | Effect |
|---|---|---|
| PRE (Preset) | LOW | Forces Q=1 immediately, ignores clock |
| CLR (Clear) | LOW | Forces Q=0 immediately, ignores clock |
These override synchronous operation and are used for initialization/reset.
Timing Parameters Summary
| Parameter | Symbol | Definition |
|---|---|---|
| Setup time | tₛ | Min time D stable before clock edge |
| Hold time | tₕ | Min time D stable after clock edge |
| Clock-to-Q delay | tₚ_CQ | Time from clock edge to Q valid |
| Min clock period | T_min | tₚ_CQ + tₛ + t_combinational |
| Max frequency | f_max | 1 / T_min |
Setup/hold violation → metastability: output oscillates and may settle to wrong value. Critical in clock-domain crossing circuits.
Master-Slave Construction
Classic edge-triggered flip-flop implementation: 1. Master (D latch, EN = CLK): captures D when CLK=1 2. Slave (D latch, EN = CLK′): transfers to output when CLK=0 (falling edge triggers)
Rising-edge flip-flop swaps the enable polarities.
D ──► [Master latch] ──internal Q_M──► [Slave latch] ──► Q
CLK CLK′