Multiplexers and Decoders

Overview

Multiplexers (MUX) and decoders are the two most versatile combinational building blocks. A MUX selects among many data inputs; a decoder activates exactly one of many outputs. Both can implement arbitrary Boolean functions.

Multiplexer Fundamentals

A 2ⁿ-to-1 MUX has: - 2ⁿ data inputs: I₀, I₁, …, I₂ⁿ⁻¹ - n select lines: S₀ … Sₙ₋₁ - 1 output: Y

Y = the data input selected by the binary value of the select lines.

2-to-1 MUX

Y = S′·I₀ + S·I₁

4-to-1 MUX

Y = S₁′S₀′·I₀ + S₁′S₀·I₁ + S₁S₀′·I₂ + S₁S₀·I₃

8-to-1 MUX (74HC151)

3 select lines (A, B, C); 8 data inputs; active-LOW enable.

MUX as a Universal Function Generator

A 2ⁿ-to-1 MUX can implement any n-variable Boolean function by connecting 0 or 1 to each data input (all n variables drive the select lines):

Example: F(A, B) = A ⊕ B using a 4-to-1 MUX (A=S₁, B=S₀):

Shannon expansion (one-variable reduction): implement an n-variable function with a 2ⁿ⁻¹-to-1 MUX by using one variable as the last select line and putting expressions (not just constants) on the data inputs.

Example: F(A,B,C) = Σm(1,2,6,7), use A,B as selects, put C-expressions on inputs:

MUX Expansion (Building Larger MUXes)

Build a 16-to-1 MUX from four 4-to-1 MUXes and one 4-to-1 MUX as the final stage:

          S₁S₀         S₃S₂ (upper select)
I₀–I₃  → MUX₀ ─────┐
I₄–I₇  → MUX₁ ──── MUX_final ──── Y
I₈–I₁₁ → MUX₂ ─────┘ (S₃S₂)
I₁₂–I₁₅→ MUX₃ ─────┘

Demultiplexer (DEMUX)

Routes one input to one of 2ⁿ outputs. A 1-to-4 DEMUX:

A decoder with the data signal on its enable line is a DEMUX.

Decoder Fundamentals

An n-to-2ⁿ decoder has n inputs and 2ⁿ outputs. Exactly one output is active at a time.

2-to-4 Decoder

Equations (active-HIGH): Yᵢ = EN · (minterm i)

3-to-8 Decoder (74HC138)

• 3 address inputs: A, B, C
• 8 active-LOW outputs: Y̅₀ – Y̅₇
• 3 enable inputs: G1 (active-HIGH), G̅2A, G̅2B (both active-LOW)
• Active when: G1=1, G̅2A=0, G̅2B=0

Y̅ᵢ = 0  when enabled and address = i
Y̅ᵢ = 1  otherwise

Decoder as Function Generator

Connect decoder outputs (minterms) to an OR gate → any SOP function.

Example: F(A,B,C) = Σm(0,3,5,6)

3-to-8 decoder:
  Y₀ ──┐
  Y₃ ──┤ OR ──── F
  Y₅ ──┤
  Y₆ ──┘

With active-LOW outputs (74HC138), use a NAND instead of OR (De Morgan).

Decoder Expansion

Build a 4-to-16 decoder from two 3-to-8 decoders:

MSB (A₃) ────────────────── EN (decoder_HIGH): selects upper 8 outputs
A₃′ ─────────────────────── EN (decoder_LOW): selects lower 8 outputs
A₂, A₁, A₀ ─── both decoders' address inputs

MUX vs Decoder Comparison

Common ICs

Tri-State Buffers and Bus MUX

Tri-state (3-state) buffer: output can be HIGH, LOW, or high-impedance (Z).

Used to share a common bus among multiple sources:

Device A ── tri-state buffer ──┐
Device B ── tri-state buffer ──┤─── shared bus
Device C ── tri-state buffer ──┘
Only one enable is asserted at a time.