Computer Architecture Cheatsheet
Instruction Set Architecture
Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.
What an ISA Defines
An ISA is the hardware-software interface contract. It specifies:
- Instruction encodings (binary formats)
- Programmer-visible register set
- Data types and sizes supported
- Memory model (addressing, alignment)
- Privilege levels and protection
- Exception and interrupt behavior
- Calling conventions (by convention, not always ISA-mandated)
RISC vs CISC
| Property | RISC | CISC |
|---|---|---|
| Instructions | Fixed-size, simple | Variable-size, complex |
| Memory access | Load/store only | Operands can be in memory |
| Registers | Many (≥32) | Fewer (x86 historically 8) |
| Cycles per instruction | Usually 1 (ideally) | 1 to many |
| Compiler complexity | Higher | Lower |
| Examples | ARM, RISC-V, MIPS | x86, x86-64, VAX |
Modern x86 CPUs internally translate CISC instructions into RISC-like micro-ops (µops), blurring the distinction.
Instruction Types
| Class | Examples | Description |
|---|---|---|
| Data transfer | MOV, LDR, SW | Register ↔ register, register ↔ memory |
| Arithmetic | ADD, SUB, MUL, DIV | Integer/FP computation |
| Logical | AND, OR, XOR, NOT | Bitwise operations |
| Shift/rotate | SHL, SHR, ROL | Bit displacement |
| Control flow | JMP, BEQ, CALL, RET | Change PC |
| Comparison | CMP, TEST | Set condition flags |
| System | SYSCALL, INT, HLT | OS interface, halt |
| SIMD | VADD, VMULPS | Parallel vector ops |
Instruction Formats
RISC-V (32-bit fixed-width, 6 formats)
R-type (register): [funct7|rs2|rs1|funct3|rd|opcode] 7 5 5 3 5 7 bits I-type (immediate): [ imm[11:0] |rs1|funct3|rd|opcode] 12 5 3 5 7 S-type (store): [imm[11:5]|rs2|rs1|funct3|imm[4:0]|opcode] B-type (branch): [imm[12|10:5]|rs2|rs1|funct3|imm[4:1|11]|opcode] U-type (upper imm): [ imm[31:12] |rd|opcode] J-type (jump): [imm[20|10:1|11|19:12]|rd|opcode]
x86-64 (variable-width, 1–15 bytes)
[Prefixes 0–4 bytes][REX 0–1][Opcode 1–3][ModRM 0–1][SIB 0–1][Disp 0–4][Imm 0–4]
- ModRM byte encodes addressing mode, source, destination
- REX prefix extends registers from 8 to 16 (r8–r15)
Addressing Modes
| Mode | Syntax | Effective address / value |
|---|---|---|
| Immediate | #5 / MOV r0, #5 | Constant 5 (no memory access) |
| Register | r1 | Value in r1 |
| Direct / Absolute | [0x1000] | Memory[0x1000] |
| Register indirect | [r1] | Memory[r1] |
| Base + offset | [r1 + 8] | Memory[r1 + 8] |
| Indexed | [r1 + r2] | Memory[r1 + r2] |
| Scaled indexed | [r1 + r2*4 + 8] | Memory[r1 + r2×4 + 8] |
| PC-relative | PC + offset | Position-independent code |
| Auto-increment | [r1++] | Memory[r1]; r1 ← r1 + 1 |
Register Files
x86-64 General-Purpose Registers
| 64-bit | 32-bit | 16-bit | 8-bit high | 8-bit low | Conventional role |
|---|---|---|---|---|---|
rax | eax | ax | ah | al | Return value, accumulator |
rbx | ebx | bx | bh | bl | Callee-saved |
rcx | ecx | cx | ch | cl | Counter, 4th arg |
rdx | edx | dx | dh | dl | Data, 3rd arg |
rsi | esi | si | — | sil | Source, 2nd arg |
rdi | edi | di | — | dil | Dest, 1st arg |
rsp | esp | sp | — | spl | Stack pointer |
rbp | ebp | bp | — | bpl | Frame pointer |
r8–r15 | r8d–r15d | r8w–r15w | — | r8b–r15b | Extra args / scratch |
RISC-V Integer Registers (ABI names)
| Reg | ABI | Role | Saved by |
|---|---|---|---|
| x0 | zero | Always 0 | — |
| x1 | ra | Return address | Caller |
| x2 | sp | Stack pointer | Callee |
| x5–x7 | t0–t2 | Temporaries | Caller |
| x8–x9 | s0–s1 | Saved registers | Callee |
| x10–x11 | a0–a1 | Args / return vals | Caller |
| x12–x17 | a2–a7 | Arguments | Caller |
| x18–x27 | s2–s11 | Saved registers | Callee |
| x28–x31 | t3–t6 | Temporaries | Caller |
Condition Codes / Flags
x86 RFLAGS relevant bits:
| Flag | Meaning | Set when |
|---|---|---|
| CF | Carry | Unsigned overflow / borrow |
| ZF | Zero | Result = 0 |
| SF | Sign | Result MSB = 1 (negative) |
| OF | Overflow | Signed overflow |
| PF | Parity | Low byte has even number of 1s |
| AF | Auxiliary carry | Carry out of bit 3 (BCD) |
Conditional jumps (x86) — selected:
| Instruction | Condition | Flags |
|---|---|---|
JE / JZ | Equal / zero | ZF = 1 |
JNE / JNZ | Not equal | ZF = 0 |
JL / JNGE | Signed less | SF ≠ OF |
JG / JNLE | Signed greater | ZF = 0 and SF = OF |
JB / JNAE | Unsigned below | CF = 1 |
JA / JNBE | Unsigned above | CF = 0 and ZF = 0 |
JS | Sign (negative) | SF = 1 |
JO | Overflow | OF = 1 |
Calling Conventions
System V AMD64 ABI (Linux / macOS x86-64)
| Role | Registers |
|---|---|
| Integer arguments (1–6) | rdi, rsi, rdx, rcx, r8, r9 |
| FP arguments (1–8) | xmm0–xmm7 |
| Return value (integer) | rax (rdx for 128-bit) |
| Return value (FP) | xmm0 |
| Caller-saved | rax, rcx, rdx, rsi, rdi, r8–r11, xmm0–xmm15 |
| Callee-saved | rbx, rbp, r12–r15 |
| Stack alignment | 16-byte aligned at call |
Stack Frame Layout (x86-64)
Higher addresses +------------------+ | caller's frame | +------------------+ | return address | ← pushed by CALL +------------------+ | saved rbp | ← PUSH rbp; MOV rbp, rsp +------------------+ | local variables | +------------------+ | outgoing args | (if > 6 integer args) +------------------+ ← rsp (16-byte aligned) Lower addresses
Privilege Levels
| Level | x86 term | Access |
|---|---|---|
| 0 (most privileged) | Ring 0 | OS kernel; all instructions & I/O |
| 1–2 | Ring 1–2 | Rarely used; drivers on some OSes |
| 3 (least privileged) | Ring 3 | User programs; no I/O, no privileged instructions |
Privileged instructions (in/out, hlt, lidt, etc.) trap to the OS if executed in Ring 3.
Memory Models
| Model | Description | Example |
|---|---|---|
| Sequential consistency | All cores see memory ops in program order | Simplest; expensive |
| Total Store Order (TSO) | Stores may be buffered; loads bypass store buffer | x86 |
| Relaxed (ARM, POWER) | Loads and stores may be reordered; fences required | ARM, RISC-V (weak) |
Memory fences / barriers (MFENCE, DMB, FENCE) prevent reordering across the barrier.