Computer Architecture Cheatsheet

The CPU

Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.

CPU Building Blocks

Unit	Function
PC (Program Counter)	Holds address of next instruction to fetch
IR (Instruction Register)	Holds the instruction currently being decoded
Register File	Array of fast on-chip storage words
ALU	Integer add, subtract, compare, logical ops
FPU	Floating-point arithmetic (may be co-processor or integrated)
Control Unit	Generates control signals to route data and sequence stages
Branch predictor	Guesses direction/target of branches before they resolve
Cache (L1 I/D)	First-level instruction and data caches
TLB	Translation Lookaside Buffer — caches virtual→physical page mappings
MMU	Memory Management Unit — performs virtual address translation

Datapath — Single-Cycle RISC

      ┌─────┐  inst   ┌────────┐  ctrl signals
  PC─►│Imem │────────►│Decode  │──────────────────────────────┐
      └─────┘         └────────┘                              │
         │ PC+4              │ rs1, rs2, rd, imm              │
         ▼                   ▼                                │
      ┌──────────────────────────┐                            │
      │        Register File     │                            │
      │  rs1─►A   B◄─rs2         │                           │
      └──────────────────────────┘                            │
            │A        │B         imm◄─────────────────────────┘
            ▼         ▼                                       │
          ┌─────────────┐                                     │
          │     ALU     │◄────── ALUSrc mux (B or imm)        │
          └─────────────┘                                     │
               │ result                                       │
               ▼                                              │
          ┌──────────┐                                        │
          │  Dmem    │ (for load/store)                       │
          └──────────┘                                        │
               │                                              │
               ▼                                              │
          ┌──────────┐                                        │
          │  WB mux  │◄── RegWrite, MemToReg ─────────────────┘
          └──────────┘
               │ write data → rd

Control Signals (RISC-V subset)

Instruction	RegWrite	ALUSrc	MemRead	MemWrite	MemToReg	Branch
`add rd,rs1,rs2`	1	0	0	0	0	0
`lw rd,off(rs1)`	1	1	1	0	1	0
`sw rs2,off(rs1)`	0	1	0	1	X	0
`beq rs1,rs2,L`	0	0	0	0	X	1
`addi rd,rs1,imm`	1	1	0	0	0	0

ALU

The ALU computes a result and sets status flags:

Operation	4-bit ALU control	Notes
AND	0000	Bitwise
OR	0001	Bitwise
ADD	0010	Signed/unsigned integer add
SUB	0110	A − B (add with B inverted + carry-in=1)
SLT (set if less than)	0111	Result = 1 if A < B, else 0
NOR	1100	Bitwise

Ripple-Carry Adder vs Carry-Lookahead

Type	Delay	Area	Note
Ripple-carry	O(n)	O(n)	Simple, slow
Carry-lookahead	O(log n)	O(n log n)	Fast, used in practice
Carry-select	O(√n)	O(n)	Pre-computes both carries

Carry-lookahead uses generate (G = A·B) and propagate (P = A⊕B) functions:

Cᵢ₊₁ = Gᵢ + Pᵢ · Cᵢ

Registers and Register Files

Implemented as an array of D flip-flops (or latches)
Read: combinational (address → output on same cycle)
Write: synchronous (on rising clock edge, if write-enable asserted)
Register 0 (RISC-V x0, MIPS $0) is hardwired to 0 — writes ignored

Branch and Jump Logic

Scenario	Action
Unconditional jump	PC ← target address
Conditional branch taken	PC ← PC + sign_extend(offset)
Conditional branch not taken	PC ← PC + 4 (next sequential)
Indirect jump / return	PC ← register value

Branch Prediction (see Pipelining for detail)

Predictor	Accuracy	Notes
Always not-taken	~60–70%	Free; loops predict wrong on entry
Static (backward taken)	~65–75%	Backward branches usually loops
1-bit (last outcome)	~80–85%	Per-branch single history bit
Bimodal (2-bit saturating counter)	~85–90%	Less sensitive to single misprediction
Correlating / two-level	~90–95%	Uses recent branch history
TAGE (modern CPUs)	~96–99%	Tagged geometric history

Execution Units in Superscalar CPUs

Modern out-of-order CPUs have multiple, heterogeneous execution units:

Unit type	Operations
Integer ALU	ADD, SUB, AND, OR, XOR, shifts, CMP
Integer multiplier	MUL, IMUL (higher latency)
Integer divider	DIV — separate, very high latency
Load unit	Memory reads, address generation
Store unit	Memory writes, address + data
FP/SIMD ALU	FADD, FSUB, FMUL, vector integer/FP
FP divider / sqrt	FDIV, FSQRT — high latency
Branch unit	Evaluates conditions, updates predictor

Reservation Stations (Tomasulo)

Instructions wait in reservation stations until all source operands are ready. Each entry holds:

Op, Qj/Qk (tags of pending results), Vj/Vk (ready values), busy bit

When a unit broadcasts its result (CDB — Common Data Bus), all waiting stations with matching tag capture the value and become ready.

Out-of-Order Execution Pipeline (Overview)

Fetch → Decode → Rename → Dispatch → Issue → Execute → Complete → Commit
                  (ROB)             (RS)               (CDB)      (retire)

Stage	Purpose
Rename	Map architectural regs → physical regs to eliminate WAR/WAW hazards
Dispatch	Place instruction in ROB (Reorder Buffer) + Reservation Station
Issue	Select ready instruction from RS, send to execution unit
Complete	Write result to physical reg, broadcast on CDB
Commit (retire)	In-order; update arch state, free ROB entry

Register Renaming

Eliminates false dependences:

Hazard	Type	Example	Resolved by renaming?
RAW (true)	Flow	`r1←r2+r3` then `r4←r1+r5`	No (real)
WAR (anti)	`r1←r2+r3` then `r2←r4+r5`	Yes
WAW (output)	`r1←r2+r3` then `r1←r4+r5`	Yes

Power and Clock

Dynamic power: P_d = α · C · V² · f (α = activity factor, C = capacitance, V = voltage, f = frequency)
Static power: P_s = I_leak · V (leakage current, grows with shrinking process nodes)
Total: P = P_d + P_s
Reducing V² is the most effective lever — but limits max frequency
DVFS (Dynamic Voltage/Frequency Scaling): OS adjusts V and f based on load (e.g., CPU P-states)