Computer Architecture Cheatsheet

Memory Hierarchy

Use this Computer Architecture reference while you build software engineering projects, review code for technical interview prep, or polish examples for a software engineer resume.

The Memory Hierarchy Principle

No single memory technology offers high speed, large capacity, and low cost simultaneously. The hierarchy exploits locality to give the illusion of both large and fast memory.

Speed ▲  Cost/bit ▲
      │
      │  Registers      ~300 ps    <1 KB   On-chip flip-flops
      │  L1 Cache       ~1 ns      32–64 KB  On-chip SRAM
      │  L2 Cache       ~4 ns      256 KB–2 MB  On-chip SRAM
      │  L3 Cache       ~10–40 ns  8–64 MB  On-die SRAM
      │  DRAM (main)    ~60–80 ns  8–256 GB  Off-chip
      │  NVMe SSD       ~100 µs    1–32 TB  PCIe attached
      │  HDD            ~10 ms     1–20 TB  Spinning disk
      │  Tape/Archive   ~sec–min   Unlimited
      ▼
Capacity ▲  Access time ▲

Locality

Type	Definition	Example
Temporal locality	A recently accessed location is likely to be accessed again soon	Loop variable accessed each iteration
Spatial locality	Accessing one location makes nearby locations likely to be accessed soon	Iterating an array sequentially

Cache design exploits both: temporal → keep recently used data in cache; spatial → fetch an entire cache line (block) at once (typically 64 bytes).

DRAM Basics

DRAM cell = 1 transistor + 1 capacitor. Charge on capacitor = 1, discharged = 0. Must be refreshed every ~64 ms or data is lost.

DRAM Timing Parameters

Parameter	Symbol	Meaning	Typical (DDR5)
CAS Latency	CL	Cycles from column address to data	40
RAS-to-CAS delay	tRCD	Cycles to open a row	40
Row Precharge	tRP	Cycles to close a row	40
Row Active Time	tRAS	Min cycles a row stays open	77
Data Rate	—	Transfers per second	6400 MT/s

DDR Generations

Gen	Voltage	Typical bandwidth per channel
DDR4	1.2 V	25.6–51.2 GB/s
DDR5	1.1 V	38.4–102.4 GB/s
LPDDR5 (mobile)	1.05 V	up to 68 GB/s
HBM3 (GPU/HPC)	—	up to 1+ TB/s

SRAM vs DRAM

Property	SRAM	DRAM
Cell size	6 transistors	1T + 1C
Speed	~1–5 ns	~50–80 ns
Density	Low	High
Refresh needed	No	Yes
Power (standby)	Low (no refresh)	Higher (refresh)
Cost/bit	High	Low
Use	Registers, caches	Main memory

Storage Technologies

Technology	Write endurance	Latency	Use
SLC NAND flash	~100 K P/E cycles	µs read, ms write	Premium SSDs, enterprise
MLC NAND	~10 K P/E	µs/ms	Consumer SSDs
TLC NAND	~3 K P/E	µs/ms	Bulk consumer SSDs
QLC NAND	~1 K P/E	µs/ms	High-density, read-heavy
3D XPoint / Optane	~millions	~10 µs	(Discontinued; was DRAM-like)
HDD (spinning)	Unlimited writes	~5–10 ms	Bulk cold storage

Memory Interleaving

Multiple DRAM banks accessed in round-robin to overlap access latency and maximize bandwidth. With k banks, can sustain k simultaneous requests.

Memory Bandwidth vs Latency

Latency = time to first byte of a random access
Bandwidth = sustained bytes/second for sequential access

Sequential access saturates bandwidth; random access is latency-bound. Example (DDR5-6400 dual-channel): - Peak bandwidth: ~100 GB/s - Latency: ~70–80 ns for a random access

NUMA (Non-Uniform Memory Access)

In multi-socket systems, each CPU socket has its own local DRAM. Accessing another socket's memory crosses a high-latency interconnect (e.g., AMD Infinity Fabric, Intel UPI).

Access type	Latency	Notes
Local NUMA node	~70 ns	Normal DRAM latency
Remote NUMA node	~120–200 ns	Cross-socket hop

OS NUMA-awareness: Linux numactl, CPU affinity scheduling, first-touch DRAM allocation policy.

Memory Coherence (Multi-Core)

When multiple cores each have their own L1/L2 caches holding copies of the same address, they must agree on the current value. The cache coherence protocol enforces this.

MESI Protocol States

State	Meaning	Can read?	Can write?	Dirty?
M odified	Only copy; differs from memory	Yes	Yes	Yes
E xclusive	Only copy; matches memory	Yes	Yes (silent → M)	No
S hared	Multiple clean copies	Yes	No (must invalidate)	No
I nvalid	Not present or invalidated	No	No	—

Transitions:

Event	State change
Read miss (no other sharer)	I → E
Read miss (other sharers exist)	I → S
Write hit in E	E → M
Write hit in S (send invalidations)	S → M
Another core reads M	M → S (writeback)
Another core writes to our S	S → I

Memory System Performance Equations

Average Memory Access Time (AMAT):

AMAT = Hit time + Miss rate × Miss penalty

For a two-level hierarchy:

AMAT = L1 hit time + L1 miss rate × (L2 hit time + L2 miss rate × Memory time)

Example: - L1: 1 cycle, 5% miss rate - L2: 10 cycles, 2% miss rate - Memory: 200 cycles

AMAT = 1 + 0.05 × (10 + 0.02 × 200) = 1 + 0.05 × 14 = 1.7 cycles